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| Freescale Semiconductor Data Sheet: Advanced Information An Energy-Efficient Solution from Freescale Document Number: MCF51MM256 Rev. 3, 04/2010 MCF51MM256/128 The MCF51MM256 series devices are members of the low-cost, low-power, high-performance ColdFire(R) V1 family of 32-bit microcontrollers (MCUs) designed for handheld metering devices. Not all features are available in all devices or packages; see Table 2 for a comparison of features by device. 32-Bit ColdFire V1 Central Processor Unit (CPU) * Up to 50.33-MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V and 20 MHz CPU above 1.8 V across temperature range of -40C to 105C. * ColdFire Instruction Set Revision C (ISA_C). * 32-bit multiply and accumulate (MAC) supports signed or unsigned integer or signed fractional inputs. On-Chip Memory * 256 K Flash comprised of two independent 128 K flash arrays; read/program/erase over full operating voltage and temperature; allows interrupt processing while programming. * 32 Kbytes System Random-access memory (RAM). * Security circuitry to prevent unauthorized access to RAM and Flash contents. Power-Saving Modes * Two ultra-low power stop modes. Peripheral clock enable register can disable clocks to unused modules to reduce currents. * Time of Day (TOD) -- Ultra low-power 1/4 sec counter with up to 64s timeout. * Ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the TOD. 6 usec typical wake up time from stop3 mode. Clock Source Options * Oscillator (XOSC1) -- Loop-control Pierce oscillator; 32.768 kHz crystal or ceramic resonator dedicated for TOD operation. * Oscillator (XOSC2) for high frequency crystal input for MCG reference to be used for system clock and USB operations. * Multipurpose Clock Generator (MCG) -- PLL and FLL; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 4 kHz to 50 MHz. System Protection * Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock. * Low-voltage detection with reset or interrupt; selectable trip points; separate low voltage warning with optional interrupt; selectable trip points. * Illegal opcode and illegal address detection with reset. * Flash block protection for each array to prevent accidental write/erasure. * Hardware CRC to support fast cyclic redundancy checks. Development Support * Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM connection supports same electrical interface used by the S08 family debug modules. * Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 data). * On-chip trace buffer provides programmable start/stop recording conditions. Peripherals * USB -- Dual-role USB On-The-Go (OTG) device, supports USB in either device, host or OTG configuration. On-chip transceiver and 3.3V regulator MCF51MM256/128 80-LQFP 12mm x 12mm 81-BGA 10mm x 10mm 100-LQFP 14mm x 14mm 104-BGA 10mm x 10mm help save system cost, fully compliant with USB Specification 2.0. Allows control, bulk, interrupt and isochronous transfers. * SCIx -- Two serial communications interfaces with optional 13-bit break; option to connect Rx input to PRACMP output on SCI1 and SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge. * SPI1 -- Serial peripheral interface with 64-bit FIFO buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting. * SPI2 -- Serial peripheral interface with full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting. * IIC -- Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing. * CMT -- Carrier Modulator timer for remote control communications. Carrier generator, modulator and driver for dedicated infrared out (IRO). Can be used as an output compare timer. * TPMx -- Two 4-channel Timer/PWM Module; Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; external clock input/pulse accumulator. * Mini-FlexBus -- Multi-function external bus interface with user programmable chip selects and the option to multiplex address and data lines. * PRACMP -- Analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3. Measurement Engine * ADC16 -- 16-bit successive approximation ADC with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V, Configurable hardware trigger for 8 Channel select and result registers. * PDB -- Programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for ADC module provides periodic coordination of ADC sampling sequence with sequence completion interrupt; Back-to-Back mode and Timed mode. * DAC -- 12-bit resolution; 16-word data buffers with configurable watermark. * OPAMPx -- 2 flexible operational amplifiers configurable for general operations; Low offset and temperature drift. * TRIAMPx -- 2 trans-impedance amplifiers dedicated for converting current inputs into voltages. Input/Output * Up to 68 GPIOs and 1 output-only pin. * Voltage Reference output (VREFO). * Dedicated infrared output pinwith high current sink capability. * Up to 16 KBI pins with selectable polarity. * Up to 16 pins of rapid general purpose I/O. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages List of Topics 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . .15 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .15 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.4 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . .18 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . .22 3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.10 MCG and External Oscillator (XOSC) Characteristics . . . .33 3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . . . . . .36 3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .45 3.17 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . . . . .47 3.18 OPAMP Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . .48 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.4 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Figure 7. Offset at Half Scale vs Temperature . . . . . . . . . . . . . 27 Figure 9. ADC Input Impedance Equivalency Diagram (MM256 16-BIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9. Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 37 Figure 10. Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . 37 Figure 11. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13. Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 14. Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . 40 Figure 15. SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . 41 Figure 16. SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . 42 Figure 17. SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 42 Figure 18. SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 43 List of Tables Table 2. MCF51MM256/128 Functional Units . . . . . . . . . . . . . . 5 Table 2. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 16 Table 6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18 Table 8. ESD and Latch-Up Protection Characteristics . . . . . . 18 Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Supply Current Characteristics . . . . . . . . . . . . . . . . . 22 Table 11. Typical Stop Mode Adders . . . . . . . . . . . . . . . . . . . . 24 Table 12. PRACMP Electrical Specifications . . . . . . . . . . . . . . 22 Table 13. DAC12LV Specifications . . . . . . . . . . . . . . . . . . . . . . 22 Table 13. DAC 12LV Operating Requirements . . . . . . . . . . . . . 26 Table 14. DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . 27 Table 16. 16-bit ADC Operating Conditions . . . . . . . . . . . . . . . 25 Table 17. MCG (Temperature Range = -40 to 105C Ambient) 33 Table 18. XOSC (Temperature Range = -40 to 105C Ambient) 35 Table 19. Mini-FlexBus AC Timing Specifications . . . . . . . . . . 36 Table 21. TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 22. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 23. Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 24. Internal USB 3.3 V Voltage Regulator Characteristics 44 Table 31. VREVREF Electrical Specifications . . . . . . . . . . . . . 59 Table 28. TRIAMP Characteristics 1.8-3.6 V, -40C~105C . . . 47 Table 29. OPAMP Characteristics 1.8-3.6 V . . . . . . . . . . . . . . . 48 Table 26. Orderable Part Number Summary . . . . . . . . . . . . . . 39 Table 31. Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. MCF51MM256/128 Block Diagran . . . . . . . . . . . . . . . .3 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Typical INL Error vs Digital Code . . . . . . . . . . . . . . . .24 2 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Table of Contents Freescale Semiconductor Figure 1. MCF51MM256/128 Block Diagran Non-Disclosure Agreement Required Preliminary -- Subject to Change 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Features 1 Features Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages The following table provides a cross-comparison of the features of the MCF51MM256/128 according to package. Table 1. MCF51MM256/128 Features by MCU and Package Feature FLASH Size (bytes) RAM Size (bytes) Pin Quantity Programmable Analog Comparator (PRACMP) Debug Module (DBG) Multipurpose Clock Generator (MCG) Inter-Integrated Communication (IIC) Interrupt Request Pin (IRQ) Keyboard Interrupt (KBI) Digital General Purpose I/O Power and Ground Pins Time Of Day (TOD) Serial Communications (SCI1) Serial Communications (SCI2) Serial Peripheral Interface (SPI1(FIFO)) Serial Peripheral Interface(SPI2) Carrier Modulator Timer Pin (IRO) TPM Input Clock Pin (TPMCLK) TPM1 Channels TPM2 Channels XOSC1 XOSC2 USB On-the-Go Mini-FlexBus Rapid GPIO Programmable Delay Block (PDB) 16-Bit SAR ADC Differential Channels2 16-Bit SAR ADC Single-Ended Channels DAC Ouput Pin (DACO) Voltage Reference Output Pin (VREFO) General Purpose Operational Amplifier (OPAMP) Trans-Impedance Amplifier (TRIAMP) 1 2 MCF51MM256 262144 32K 104 yes yes yes yes yes 16 100 yes yes yes yes yes 16 65 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes yes 16 yes 4 8 yes yes yes yes 81 yes yes yes yes yes 16 48 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes DATA 9 yes 4 8 yes yes yes yes 80 yes yes yes yes yes 16 47 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes DATA 9 yes 4 8 yes yes yes yes MCF51MM128 131072 32K 81 yes yes yes yes yes 16 48 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes DATA 9 yes 4 8 yes yes yes yes 80 yes yes yes yes yes 16 47 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes DATA 9 yes 4 8 yes yes yes yes 1 69 14 8 yes yes yes yes yes yes yes 4 4 yes yes yes yes 16 yes 4 8 yes yes yes yes Dedicated Analog Input Pins MEASUREMENT ENGINE Port I/O count does not include BLMS, BKGD and IRQ. BLMS and BKGD are Output only, IRQ is input only. Each differential channel is comprised of 2 pin inputs. 4 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Features The following table describes the functional units of the MCF51MM256/128. Table 2. MCF51MM256/128 Functional Units Unit Function DAC (digital to analog converter) -- Used to output voltage levels. 16-BIT SAR ADC (analog-to-digital converter) -- Measures analog voltages at up to 16 bits of resolution. The ADC has up to four differential and 8 single-ended inputs. Measurement Engine OPAMP -- General purpose op amp used for signal filtering or amplification. TRIAMP --- Transimpedance amplifier optimized for converting small currents into voltages. Measurement Engine PDB -- The measurement engine PDB is used to precisely trigger the DAC and the ADC modules to complete sensor biasing and measuring. Mini-FlexBus USB On-the-Go CMT (Carrier Modulator Timer) MCG (Multipurpose Clock Generator) Provides expansion capability for off-chip memory and peripherals. Supports the USB On-the-Go dual-role controller. Infrared output used for the Remote Controller operation. Provides clocking options for the device, including a phase-locked loop (PLL) and frequency-locked loop (FLL) for multiplying slower reference clock sources. Provides single pin debugging interface (part of the V1 ColdFire core). Executes programs and interrupt handlers. Analog comparators for comparing external analog signals against each other, or a variety of reference levels. Software Watchdog. Single-pin high-priority interrupt (part of the V1 ColdFire core). High-speed CRC calculation. Provides debugging and emulation capabilities (part of the V1 ColdFire. core) Provides storage for program code, constants, and variables. Supports standard IIC communications protocol and SMBus. Controls and prioritizes all device interrupts. Keyboard Interfaces 1 and 2. Provides an interrupt to theColdFire V1 CORE in the event that the supply voltage drops below a critical value. The LVD can also be programmed to reset the device upon a low voltage event. The Voltage Reference output is available for both on- and off-chip use. Provides stack and variable storage. Allows for I/O port access at CPU clock speeds. RGPIO is used to implement GPIO functionality. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 5 BDM (Background Debug Module) CF1 CORE (V1 ColdFire Core) PRACMP COP (Computer Operating Properly) IRQ (Interrupt Request) CRC (Cyclic Redundancy Check) DBG (Debug) FLASH (Flash Memory) IIC (Inter-integrated Circuits) INTC (Interrupt Controller) KBI1 & KBI2 LVD (Low-voltage Detect) VREF (Voltage Reference) RAM (Random-Access Memory) RGPIO (Rapid General-purpose Input/output) Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Features Table 2. MCF51MM256/128 Functional Units (continued) Unit SCI1, SCI2 (Serial Communications Interfaces) SIM (system integration unit) SPI1 (FIFO), SPI2 (Serial Peripheral Interfaces) TPM1, TPM2 (Timer/PWM Module) VREG (Voltage Regulator) SPI1 and SPI2 provide standard master/slave capability. SPI contains a FIFO buffer in order to increase the throughput for this peripheral. Timer/PWM module can be used for a variety of generic timer operations as well as pulse-width modulation. Controls power management across the device. Function Serial communications UARTs capable of supporting RS-232 and LIN protocols. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages These devices incorporate redundant crystal oscillators. One is XOSC1 and XOSC2 (Crystal Oscillators) intended primarily for use by the TOD, and the other by the CPU and other peripherals. 6 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments 2 2.1 1 A Pinouts and Pin Assignments 104-Pin MAPBGA 2 PTF7 The following figure shows the 104-pin MAPBGA pinout configuration. 3 USB_DP 4 USB_DM 5 VUSB33 6 PTF4 7 PTF3 8 FB_AD12 9 PTJ7 10 PTJ5 11 PTJ4 PTF6 A B PTG0 PTA0 PTG3 VBUS PTF5 PTJ6 PTH0 PTE5 PTF0 PTF1 PTF2 B C IRO PTG4 PTA6 PTG2 PTG6 PTG5 PTG7 PTH1 PTE4 PTE6 PTE7 C D PTA5 PTA4 PTB1 VDD1 VDD2 VDD3 PTA1 PTE3 PTE2 D E VSSA PTA7 PTB0 PTA2 PTJ3 PTE1 E F G VREFL INP1- INP2- PTG1 PTC7 PTJ2 PTJ0 PTJ1 F TRIOUT1 OUT1 OUT2 PTD5 PTD7 PTE0 G H VINP1 VINN1 PTA3 VSS1 VSS2 VSS3 PTD4 PTD3 PTD2 H J DADP0 DADM0 PTH7 PTH6 PTH4 PTH3 PTH2 PTD6 PTC2 PTC0 PTC1 J K VINP2 VINN2 DADP1 PTH5 PTB6 PTB7 PTC3 PTD1 PTC4 PTC5 PTC6 K L TRIOUT2 DACO DADM1 VREFO VREFH VDDA PTB3 PTB2 PTD0 PTB5 PTB4 L 1 2 3 4 5 6 7 8 9 10 11 Figure 2. 104-Pin MAPBGA Freescale Semiconductor 7 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Pinouts and Pin Assignments 2.2 100-Pin LQFP Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages PTJ4/RGPIOP15/FB_AD16 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTF1/RX2/USB_DP_DOWN/TPM2CH1 The following figure shows the 100-pin LQFP pinout configuration. PTE7/USB_VBUSVLD/TPM2CH3 PTE6/FB_RW/USB_SESSEND/RX2 PTE5/FB_D7/USB_SESSVLD/TX2 VDD3 VSS3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6/FB_AD8 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTJ3/RGPIOP12/FB_AD5 PTJ2/FB_AD4 PTJ1/FB_AD3 PTJ0/FB_AD2 PTE0/KBI2P3/FB_ALE/FB_CS1 PTD7/USB_PULLUP(D+)/RX1 PTD6/USB_ALTCLK/TX1 PTD5/SCL/RGPIOP11/TPM1CH3 PTD4/SDA/RGPIOP10/TPM1CH2 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2/FB_D0/FB_AD1 PTC0/MOSI2/FB_OE/FB_CS0 PTH5/RGPIOP5/FB_D4 PTH6/RGPIOP6/FB_D3 PTH7/RGPIOP7/FB_D2 PTF5/KBI2P7/FB_D3/FB_AD9 PTF4/SDA/FB_D4/FB_AD10 PTF3/SCL/FB_D5/FB_AD11 FB_AD12 PTJ7/FB_AD13 PTJ6/FB_AD14 PTJ5/FB_AD15 PTA0/FB_D2/SS1 IRO PTG5/FB_RW PTG6/FB_AD19 PTG7/FB_AD18 PTH0/FB_OE PTH1/FB_D0 PTA1/KBI1P0/TX1/FB_D1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/FB_D6/ADP5 PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1 TRIOUT1/DADP2VINP1 VINN1/DADM2 INP2OUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TRIOUT/DADP3 VINP2 VINN2/DADM3 Figure 3. 100-Pin LQFP 8 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTH2/RGPIOP2/FB_D7 PTH3/RGPIOP3/FB_D6 PTH4/RGPIOP4/FB_D5 VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 DADP0 DADM0 VREFO DADP1 DADM1 VREFH DACO PTB5/XTAL2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 LQFP PTF0/USB_ID/TPM2CH2 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VSS1 VBUS USB_DP USB_DM VUSB33 VDD1 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments 2.3 81-Pin MAPBGA Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 9 The following figure shows the 81-pin MAPBGA pinout configuration. 1 A IRO 2 PTG0 3 PTF6 4 USB_DP 5 VBUS 6 VUSB33 7 PTF4 8 PTF3 9 PTE4 A B PTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 B C PTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 C D INP1- PTA7 PTB0 PTB1 PTA2 PTA3 PTD5 PTD7 PTE0 D E OUT1 VINN1 OUT2 VDD2 VDD3 VDD1 PTD2 PTD3 PTD6 E F VINP1 TRIOUT1 INP2- VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 F G DADP0 DACO TRIOUT2 VINN2 VREFO PTB6 PTC0 PTC1 PTC2 G H DADM0 DADM1 DADP1 VINP2 PTC3 PTC4 PTD0 PTC5 PTC6 H J VSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 J 1 2 3 4 5 6 7 8 9 Figure 4. 81-Pin MAPBGA Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments 2.4 80-Pin LQFP Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF5/KBI2P7/FB_D3/FB_AD9 PTF4/SDA/FB_D4/FB_AD10 PTF3/SCL/FB_D5/FB_AD11 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTF1/RX2/USB_DP_DOWN/TPM2CH1 PTF0/USB_ID/TPM2CH2 PTE7/USB_VBUSVLD/TPM2CH3 PTE6/FB_RW/USB_SESSEND/RX2 PTE5/FB_D7/USB_SESSVLD/TX2 VDD3 VSS3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 The following figure shows the 80-pin LQFP pinout configuration. PTA0/FB_D2/SS1 IRO PTA1/KBI1P0/TX1/FB_D1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/FB_D6/ADP5 PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1 TRIOUT1/DADP2VINP1 VINN1DADM2 INP2OUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6/FB_AD8 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTE0/KBI2P3/FB_ALE/FB_CS1 PTD7/USB_PULLUP(D+)/RX1 PTD6/USB_ALTCLK/TX1 PTD5/SCL/RGPIOP11/TPM1CH3 PTD4/SDA/RGPIOP10/TPM1CH2 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2/FB_D0/FB_AD1 10 DACO TRIOUT/DADP3 VINP2 VINN2/DADM3 DADP0 DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTC0/MOSI2/FB_OE/FB_CS0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 5. 80-Pin LQFP Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments 2.5 Pin Assignments Table 3. Package Pin Assignments Package Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 11 104 MAPBGA 81 MAPBGA 100 LQFP 80 LQFP Default Function Alternate 1 Alternate 2 Alternate 3 Composite Pin Name B2 C1 C6 C5 C7 B7 C8 D9 E9 H3 D2 D1 C3 E2 E3 D3 E1 F1 F2 G2 G1 H1 H2 F3 G3 L2 L1 K1 K2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 B2 A1 -- -- -- -- -- C4 D5 D6 C1 C2 C3 D2 D3 D4 J1 J2 D1 E1 F2 F1 E2 F3 E3 G2 G3 H4 G4 1 2 -- -- -- -- -- 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PTA0 IRO PTG5 PTG6 PTG7 PTH0 PTH1 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 PTB0 PTB1 VSSA VREFL INP1OUT1 DADP2 VINP1 DADM2 INP2OUT2 DACO DADP3 VINP2 DADM3 FB_D2 -- FB_RW FB_AD19 FB_AD18 FB_OE FB_D0 KBI1P0 KBI1P1 KBI1P2 INP1+ -- -- INP2+ -- BLMS -- -- -- -- TRIOUT1 -- VINN1 -- -- -- TRIOUT2 -- VINN2 SS1 -- -- -- -- -- -- TX1 RX1 FB_D6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FB_D1 ADP4 ADP5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PTA0/FB_D2/SS1 IRO PTG5/FB_RW PTG6/FB_AD19 PTG7/FB_AD18 PTH0/FB_OE PTH1/FB_D0 PTA1/KBI1P0/TX1/FB_D1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/FB_D6/ADP5 PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1 DADP2/TRIOUT1 VINP1 DADM2/VINN1 INP2OUT2 DACO DADP3/TRIOUT2 VINP2 DADM3/VINN2 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments Table 3. Package Pin Assignments Package 100 LQFP 80 LQFP Default Function Alternate 1 Alternate 2 Alternate 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 104 MAPBGA 81 MAPBGA Composite Pin Name J1 J2 L4 K3 L3 L5 L6 H6 L8 L7 D6 L11 L10 K5 K6 J7 J6 J5 K4 J4 J3 J10 J11 J9 K7 K9 K10 K11 F8 L9 K8 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 G1 H1 G5 H3 H2 J3 J4 F4 J5 J6 E4 J8 J9 G6 F7 -- -- -- -- -- -- G7 G8 G9 H5 H6 H8 H9 F8 H7 J7 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 -- -- -- -- -- -- 40 41 42 43 44 45 46 47 48 49 DADP0 DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2 PTB3 VDD2 PTB4 PTB5 PTB6 PTB7 PTH2 PTH3 PTH4 PTH5 PTH6 PTH7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 -- -- -- -- -- -- -- -- EXTAL1 XTAL1 -- EXTAL2 XTAL2 KBI1P3 KBI1P4 RGPIOP2 RGPIOP3 RGPIOP4 RGPIOP5 RGPIOP6 RGPIOP7 MOSI2 MISO2 KBI1P5 KBI1P6 KBI1P7 KBI2P0 KBI2P1 KBI2P2 BKGD CMPP2 -- -- -- -- -- -- -- -- -- -- -- -- -- RGPIOP0 RGPIOP1 FB_D7 FB_D6 FB_D5 FB_D4 FB_D3 FB_D2 FB_OE FB_D0 SPSCK2 SS2 CMPP0 CMPP1 PRACMPO CLKOUT MS RESET -- -- -- -- -- -- -- -- -- -- -- -- -- FB_AD17 FB_AD0 -- -- -- -- -- -- FB_CS0 FB_AD1 ADP6 ADP7 ADP8 ADP9 ADP10 ADP11 -- -- DADP0 DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3/RGPIOP0/FB_AD17 PTB7/KBI1P4/RGPIOP1/FB_AD0 PTH2/RGPIOP2/FB_D7 PTH3/RGPIOP3/FB_D6 PTH4/RGPIOP4/FB_D5 PTH5/RGPIOP5/FB_D4 PTH6/RGPIOP6/FB_D3 PTH7/RGPIOP7/FB_D2 PTC0/MOSI2/FB_OE/FB_CS0 PTC1/MISO2/FB_D0/FB_AD1 PTC2/KBI1P5/SPSCK2/ADP6 PTC3/KBI1P6/SS2/ADP7 PTC4/KBI1P7/CMPP0/ADP8 PTC5/KBI2P0/CMPP1/ADP9 PTC6/KBI2P1/PRACMPO/ADP10 PTC7/KBI2P2/CLKOUT/ADP11 PTD0/BKGD/MS PTD1/CMPP2/RESET 12 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments Table 3. Package Pin Assignments Package 100 LQFP 80 LQFP Default Function Alternate 1 Alternate 2 Alternate 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 104 MAPBGA 81 MAPBGA Composite Pin Name H11 H10 H9 G9 J8 G10 G11 F10 F11 F9 E10 E11 D11 D10 C9 H8 D8 B8 C10 C11 B9 B10 B11 A11 A10 B6 A9 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 E7 E8 F9 D7 E9 D8 D9 -- -- -- -- C9 C8 B9 A9 F5 E5 C7 C6 B6 B8 B7 C5 -- -- -- -- 50 51 52 53 54 55 56 -- -- -- -- 57 58 59 60 61 62 63 64 65 66 67 68 -- -- -- -- PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 PTE0 PTJ0 PTJ1 PTJ2 PTJ3 PTE1 PTE2 PTE3 PTE4 VSS3 VDD3 PTE5 PTE6 PTE7 PTF0 PTF1 PTF2 PTJ4 PTJ5 PTJ6 PTJ7 USB_ALTCLK USB_PULLUP (D+) SDA SCL USB_ALTCLK USB_PULLUP (D+) KBI2P3 FB_AD2 FB_AD3 FB_AD4 RGPIOP12 KBI2P4 KBI2P5 KBI2P6 CMPP3 -- -- FB_D7 FB_RW USB_ VBUSVLD USB_ID RX2 TX2 RGPIOP15 FB_AD15 FB_AD14 FB_AD13 RGPIOP8 RGPIOP9 TPM1CH0 PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0 TPM1CH1 PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1 PTD4/SDA/RGPIOP10/TPM1CH2 PTD5/SCL/RGPIOP11/TPM1CH3 PTD6/USB_ALTCLK/TX1 PTD7/USB_PULLUP(D+) /RX1 PTE0/KBI2P3/FB_ALE/FB_CS1 PTJ0/FB_AD2 PTJ1/FB_AD3 PTJ2/FB_AD4 PTJ3/RGPIOP12/FB_AD5 PTE1/KBI2P4/RGPIOP13/FB_AD6 PTE2/KBI2P5/RGPIOP14/FB_AD7 PTE3/KBI2P6/FB_AD8 PTE4/CMPP3/TPMCLK/IRQ VSS3 VDD3 PTE5/FB_D7/USB_SESSVLD/TX2 PTE6/FB_RW/USB_SESSEND/RX2 PTE7/USB_VBUSVLD/TPM2CH3 PTF0/USB_ID/TPM2CH2 PTF1/RX2/USB_DP_DOWN/TPM2CH1 PTF2/TX2/USB_DM_DOWN/TPM2CH0 PTJ4/RGPIOP15/FB_AD16 PTJ5/FB_AD15 PTJ6/FB_AD14 PTJ7/FB_AD13 RGPIOP10 TPM1CH2 RGPIOP11 TPM1CH3 TX1 RX1 FB_ALE -- -- -- FB_AD5 RGPIOP13 RGPIOP14 FB_AD8 TPMCLK -- -- USB_ SESSVLD USB_ SESSEND TPM2CH3 TPM2CH2 -- -- FB_CS1 -- -- -- -- FB_AD6 FB_AD7 -- IRQ -- -- TX2 RX2 -- -- USB_DP_D TPM2CH1 OWN USB_DM_ TPM2CH0 DOWN FB_AD16 -- -- -- -- -- -- -- Freescale Semiconductor 13 Non-Disclosure Agreement Required Preliminary -- Subject to Change Pinouts and Pin Assignments Table 3. Package Pin Assignments Package 100 LQFP 80 LQFP Default Function Alternate 1 Alternate 2 Alternate 3 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 104 MAPBGA 81 MAPBGA Composite Pin Name A8 A7 A6 B5 A5 A4 A3 B4 H4 D4 A1 A2 B1 F4 C4 B3 C2 88 89 90 91 92 93 94 95 96 97 98 99 100 -- -- -- -- -- A8 A7 B5 A6 B4 A4 A5 F6 E6 A3 B1 A2 A1 -- -- -- -- 69 70 71 72 73 74 75 76 77 78 79 80 -- -- -- -- FB_AD12 PTF3 PTF4 PTF5 VUSB33 USB_DM USB_DP VBUS VSS1 VDD1 PTF6 PTF7 PTG0 PTG1 PTG2 PTG3 PTG4 -- SCL SDA KBI2P7 -- -- -- -- -- -- MOSI1 MISO1 SPSCK1 USB_ SESSEND USB_DM_ DOWN USB_DP_ DOWN USB_SESSVLD -- FB_D5 FB_D4 FB_D3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- FB_AD11 FB_AD10 FB_AD9 -- -- -- -- -- -- -- -- -- -- -- -- -- FB_AD12 PTF3/SCL/FB_D5/FB_AD11 PTF4/SDA/FB_D4/FB_AD10 PTF5/KBI2P7/FB_D3/FB_AD9 VUSB33 USB_DM USB_DP VBUS VSS1 VDD1 PTF6/MOSI1 PTF7/MISO1 PTG0/SPSCK1 PTG1/USB_SESSEND PTG2/USB_DM_DOWN PTG3/USB_DP_DOWN PTG4/USB_SESSVLD 14 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 3 Preliminary Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages This section contains electrical specification tables and reference timing diagrams for the MCF51MM256/128 microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 3.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 4. Parameter Classifications P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. T D NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 3.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. Freescale Semiconductor 15 Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 5. Absolute Maximum Ratings # 1 2 3 4 5 1 Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range Symbol VDD IDD VIn ID Tstg Value -0.3 to +3.8 120 -0.3 to VDD + 0.3 25 -55 to 150 Unit V mA V mA C 2 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. All functional non-supply pins are internally clamped to VSS and VDD. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. 16 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Table 6. Thermal Characteristics # 1 Symbol TA Rating Operating temperature range (packaged): MCF51MM256 MCF51MM128 2 3 TJM JA Maximum junction temperature Thermal resistance Single-layer board -- 1s 104-pin MBGA 100-pin LQFP 81-pin MBGA 80-pin LQFP 4 JA Thermal Four-layer board -- 2s2p 104-pin MBGA 100-pin LQFP 81-pin MBGA 80-pin LQFP 1 Value Unit C -40 to 105 -40 to 105 150 C C/W 67 53 67 53 C/W 39 41 39 39 1,2,3,4 resistance1, 2, 3, 4 2 3 4 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Junction to Ambient Natural Convection 1s -- Single layer board, one signal layer 2s2p -- Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Eqn. 2 Freescale Semiconductor 17 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Solving Equation 1 and Equation 2 for K gives: Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.4 ESD Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 7. ESD and Latch-up Test Conditions Model Series Resistance Human Body Storage Capacitance Number of Pulse per pin Series Resistance Machine Storage Capacitance Number of Pulse per pin Minimum input voltage limit Latch-up Maximum input voltage limit -- 7.5 V Description Symbol R1 C -- R1 C -- -- Value 1500 100 3 0 200 3 -2.5 Unit pF -- pF -- V Table 8. ESD and Latch-Up Protection Characteristics # 1 2 3 4 Rating Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current at TA = 125C Symbol VHBM VMM VCDM ILAT Min 2000 200 500 100 Max -- -- -- -- Unit V V V mA C T T T T 18 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 3.5 DC Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table 9. DC Characteristics Num 1 2 Symbol -- VOH Characteristic Operating Voltage Output high voltage Condition -- All I/O pins, low-drive strength 1.8 V, ILoad = -600 A All I/O pins, high-drive strength 2.7 V, ILoad = -10 mA 2.3 V, ILoad = -6 mA VDD - 0.5 VDD - 0.5 -- -- -- -- -- -- V V V P T C VDD - 0.5 -- -- V C Min 1.82 Typ1 -- Max 3.6 Unit V C -- 1.8V, ILoad = VDD - -3 mA 0.5 3 IOHT Output high current Max total IOH for all ports -- 4 VOL Output low voltage All I/O pins, low-drive strength 1.8 V, ILoad = 600 A All I/O pins, high-drive strength 2.7 V, ILoad = 10 mA 2.3 V, ILoad = 6 mA 1.8 V, ILoad = 3 mA 5 6 IOLT VIH Output low current Input high voltage Max total IOL for all ports all digital inputs VDD > 2.7 V VDD > 1.8 V 0.70 x VDD 0.85 x VDD -- -- -- -- -- -- -- -- 100 mA D -- 0.5 V C -- -- -- -- 0.5 0.5 0.5 100 V V V mA P T C D -- -- -- -- V V P C Freescale Semiconductor 19 Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 9. DC Characteristics (continued) Num 7 Symbol VIL Input low voltage Characteristic all digital inputs VDD > 2.7 V VDD >1.8 V 8 9 10 Vhys |IIn| |IOZ| Input hysteresis Input leakage current Hi-Z (off-state) leakage current Leakage current for analog output pins (DACO, VREFO, and OUTx, TRIOUTx) Pull-up resistors Internal pull-down resistors3 DC injection current 4, 5, 6 Single pin limit VSS > VIN > VDD -0.2 -- 0.2 mA D all digital inputs -- -- -- 0.06 x VDD -- -- -- -- -- -- -- 0.35 x VDD 0.30 x VDD -- 0.25 (TBD) 0.25 V V mV A A P C C P P P Condition Min Typ1 Max Unit C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages all input only pins VIn = VDD or VSS (Per pin) all input/output VIn = VDD or (per pin) VSS all input/output VIn = VDD or VSS (per pin) all digital inputs, when enabled -- -- 11 |IOZ| -- -- 0.5 A 12 13 14 RPU RPD IIC 17.5 17.5 -- -- 52.5 52.5 k k P P Total MCU limit, includes sum of all stressed pins VSS > VIN > VDD 15 16 17 18 19 CIn VRAM VPOR tPOR VLVDH8 Input Capacitance, all pins RAM retention voltage POR re-arm voltage7 -- -- -- -- VDD falling -- VDD rising -- 20 VLVDL Low-voltage detection threshold -- low range14 VDD falling -- VDD rising -- 1.86 1.90 1.99 V P 1.80 1.82 1.91 V P 2.16 2.21 2.27 V P 2.11 2.16 2.22 V P -5 -- -- 0.9 10 -- -- 0.6 1.4 -- 5 8 1.0 1.79 -- mA pF V V s D C C C D POR re-arm time Low-voltage detection threshold -- high range9 20 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 9. DC Characteristics (continued) Num 21 Symbol VLVWH Characteristic Low-voltage warning threshold -- high range14 VDD falling -- VDD rising -- 22 VLVWL Low-voltage warning threshold -- low range14 VDD falling 2.36 2.46 2.56 V P 2.36 2.46 2.56 V P Condition Min Typ1 Max Unit C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages -- VDD rising -- 23 24 1 2 2.11 2.16 2.22 V P 2.16 -- 1.145 2.21 50 1.17 2.27 -- 1.195 V mV V P C P Vhys VBG Low-voltage inhibit reset/recover Bandgap Voltage Reference10 hysteresis14 -- -- 3 4 5 6 Typical values are measured at 25C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. Measured with VIn = VDD. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. Run at 1 MHz bus frequency Low voltage detection and warning limits measured at 1 MHz bus frequency. Factory trimmed at VDD = 3.0 V, Temp = 25C 7 8 9 10 Freescale Semiconductor 21 Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 3.6 # Supply Current Characteristics Table 10. Supply Current Characteristics Symbol Parameter Run supply current Bus Freq VDD (V) Typ1 Max Unit Temp (C) C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 1 RIDD FEI mode All modules ON 25.165 MHz 25.165 MHz 20 MHz 8 MHz 1 MHz -40 to 25 105 -40 to 105 -40 to 105 -40 to 105 3 3 3 3 3 43 43 31.6 15.4 2.9 48 48 -- -- -- mA mA mA mA mA P P T T T 2 RIDD Run supply current FEI mode; All modules OFF 25.165 MHz 20 MHz 8 MHz 1 MHz -40 to 105 -40 to 105 -40 to 105 -40 to 105 3 3 3 3 28.1 23.2 12.3 2.4 29.6 -- -- -- mA mA mA mA C T T T 3 RIDD Run supply current LPS=0; All modules OFF 16 kHz FBILP 16 kHz FBELP -40 to 105 -40 to 105 3 3 TBD TBD -- -- A A T T 4 RIDD Run supply current LPS=1, all modules OFF 16 kHz FBELP 16 kHz FBELP 3 3 TBD TBD -- -- A A 0 to 70 -40 to 105 T T 22 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 10. Supply Current Characteristics (continued) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 23 # Symbol Parameter Bus Freq VDD (V) Typ1 Max Unit Temp (C) C 5 WIDD Wait mode FEI mode, all modules OFF supply current 25.165 MHz 20 MHz 8 MHz 1 MHz Stop2 mode supply current N/A N/A N/A N/A N/A N/A N/A N/A Stop3 mode supply current 3 3 3 3 2 2 2 2 0.410 3.5 10 21 0.410 3.4 9.5 20 0.640 10 20 31.5 0.640 9 18 30 A A A A A A A A -40 to 25 70 85 105 -40 to 25 70 85 105 P C C P C C C C 3 3 3 3 5 TBD TBD TBD -- -- -- -- mA mA mA mA -40 to 105 -40 to 105 -40 to 105 -40 to 105 C T T T 6 S2IDD 7 S3IDD No clocks active N/A N/A N/A N/A N/A N/A N/A N/A 3 3 3 3 2 2 2 2 0.650 7.1 20 37 0.400 7.1 18 33 1.2 18 28 63 0.900 16 26 59 A A A A A A A A -40 to 25 70 85 105 -40 to 25 70 85 105 P C C P C C C C Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Table 11. Typical Stop Mode Adders Temperature (C) # 1 2 3 4 5 6 7 8 1 Parameter LPO EREFSTEN IREFSTEN1 TOD LVD1 ACMP ADC1 DAC1 1 Condition -40 -- RANGE = HGO = 0 -- Does not include clock source current LVDSE = 1 Not using the bandgap (BGBE = 0) ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) High power mode; no load on DACO 50 600 (TBD) 68 50 114 18 75 500 25 75 650 (TBD) 70 75 115 20 85 500 70 100 750 (TBD) 77 100 123 23 100 500 85 150 850 (TBD) 86 150 135 33 115 500 105 250 1000 (TBD) 120 250 170 65 165 500 Units nA nA A nA A A A A C D D T D T T T T Not available in stop2 mode. 24 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Figure 6. Stop IDD versus Temperature 3.7 PRACMP Electricals Table 12. PRACMP Electrical Specifications # 1 2 3 4 5 6 7 8 9 Characteristic Supply voltage Supply current (active) (PRG enabled) Supply current (active) (PRG disabled) Supply current (ACMP and PRG all disabled) Analog input voltage Analog input offset voltage Analog comparator hysteresis Analog input leakage current Analog comparator initialization delay Symbol VPWR IDDACT1 IDDACT2 IDDDIS VAIN VAIO VH IALKG tAINIT Min 1.8 -- -- -- VSS - 0.3 -- 3.0 -- -- Typical -- -- -- -- -- 5 -- -- -- Max 3.6 60 40 2 VDD 40 20.0 1 1.0 Unit V A A nA V mV mV nA s C P C C D -- T T D T Freescale Semiconductor 25 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Table 12. PRACMP Electrical Specifications # 10 11 12 13 Characteristic Programmable reference generator inputs Programmable reference generator setup delay Programmable reference generator step size Programmable reference generator voltage range Symbol VIn2(VDD25) tPRGST Vstep Vprgout Min 1.8 -- -0.25 VIn/32 Typical -- 1 1 -- Max 2.75 -- 0.25 Vin Unit V s LSB V C -- D D P Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 3.8 12-bit DAC Electricals Table 13. DAC 12LV Operating Requirements # 1 2 3 Characteristic Supply voltage Reference voltage Temperature Symbol VDDA VDACR TA Min 1.8 1.15 -40 Max 3.6 3.6 105 Unit V V C C P C C A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Notes 4 Output load capacitance CL -- 100 pF C 5 Output load current IL -- 1 mA C 26 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics # 1 2 3 Characteristic Resolution Supply current low-power mode Supply current high-power mode Full-scale Settling time (0.5 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) low-power mode Full-scale Settling time (0.5 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) high-power mode Code-to-code Settling time (0.5 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) low-power mode Code-to-code Settling time (0.5 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) high-power mode DAC output voltage range low (high-power mode, no load, DAC set to 0) DAC output voltage range high (high-power mode, no load, DAC set to 0x0FFF) Integral non-linearity error Differential non-linearity error VDACR is > 2.4 V Offset error Gain error Power supply rejection ratio VDD 2.4 V Temperature drift of offset voltage (DAC set to 0x0800) Offset aging coefficient Symbol N IDDA_DACLP IDDA_DACHP Min Max Unit C C C C Notes 12 50 120 12 100 500 (TBD) 200 (TBD) bit A A 4 TsFSLP -- s C 5 TsFSHP -- 30 s C TsC-CLP -- 5 6 s C 7 TsC-CHP -- 1 (TBD) s C 8 Vdacoutl Vdacouth INL DNL EO EG PSRR -- VDAC R-100 -- -- -- -- 100 (TBD) mV C 9 10 11 12 13 14 -- 10 1 0.5 0.5 (TBD) -- mV LSB LSB %FS R %FS R dB mV V/yr C C C C C C See Typical Drift figure that follows. 60 15 16 Tco Ac -- -- 2(TBD) TBD C C Figure 7. Offset at Half Scale vs Temperature Freescale Semiconductor 27 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Table 14. DAC 12-Bit Operating Behaviors Preliminary Electrical Characteristics Table 15. 16-bit ADC Operating Conditions # 1 2 3 4 5 6 7 8 Symb VDDAD VDDAD VSSAD VREFH VREFL VADIN CADIN RADIN Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance Input Resistance 16-bit modes 8/10/12-bit modes Characteristic Supply voltage Conditions Absolute Delta to VDD (VDD-VDDAD)2 Delta to VSS (VSS-VSSAD)2 Min 1.8 -100 -100 1.13 VSSAD VREFL -- -- Typ1 -- 0 0 Max 3.6 +100 +100 Unit V mV mV V V V pF k C D D D D D D C C Comment VDDAD VDDAD VSSAD VSSAD -- 8 4 2 VREFH 10 5 5 28 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 3.9 ADC Characteristics Preliminary Electrical Characteristics Table 15. 16-bit ADC Operating Conditions (continued) # Symb Characteristic Analog Source Resistance 16-bit mode fADCK > 8 MHz 4 MHz < fADCK < 8 MHz fADCK < 4 MHz 13/12-bit mode fADCK > 8 MHz 4 MHz < fADCK < 8 MHz fADCK < 4 MHz 11/10-bit mode fADCK > 8 MHz 4 MHz < fADCK < 8 MHz fADCK < 4 MHz 9/8-bit mode fADCK > 4 MHz fADCK < 4 MHz 10 fADCK ADC Conversion Clock Freq. High Speed (ADLPC=0, ADHSC=1) High Speed (ADLPC=0, ADHSC=0) Low Power (ADLPC=1, ADHSC=1) C Conditions Min Typ1 Max Unit C Comment External to MCU Assumes ADLSMP=0 -- -- -- -- -- -- -- -- -- -- -- 1.0 -- -- -- -- -- -- -- -- -- -- -- -- 0.5 1 2 1 2 5 2 5 10 5 10 8.0 k k k k k k k k k k k MHz Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 9 RAS C C C C C C C C C C D 1.0 -- 5.0 MHz D 1.0 -- 2.5 MHz D 1 2 Typical values assume VDDAD = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. DC potential difference. Freescale Semiconductor 29 Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT ZAS RAS Pad leakage due to input protection SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + - CAS - RADIN INPUT PIN RADIN INPUT PIN RADIN CADIN INPUT PIN Figure 8. ADC Input Impedance Equivalency Diagram 30 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Characteristic Conditions1 ADLPC=1, ADHSC=0 Symb Min -- -- Typ2 215 470 610 0.01 2.4 5.2 6.2 Max -- -- -- -- -- -- -- Unit C Comment Supply Current ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 IDDAD IDDAD -- -- -- -- A A T C ADLSMP=0 ADCO=1 Supply Current ADC Asynchronous Clock Source Sample Time Conversion Time Total Unadjusted Error Stop, Reset, Module Off ADLPC=1, ADHSC=0 ADLPC=0, ADHSC=0 ADLPC=0, ADHSC=1 fADACK -- MHz P tADACK = 1/fADACK See Block Guide for sample times See Block Guide for conversion times 32x Hardware Averaging (AVGE = %1 AVGS = %11) 16-bit differential mode 16-bit single-ended mode TUE -- -- 16 20 +48/-40 +56/-28 LSB3 T 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Differential Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral Non-Linearity 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode INL DNL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.5 1.75 0.7 0.8 0.5 0.5 2.5 2.5 0.7 0.7 0.5 0.5 0.2 0.2 6.0 10.0 1.0 1.0 0.5 0.5 0.3 0.3 3.0 3.5 1.5 1.5 1.0 1.0 +5/-3 +5/-3 1 1 0.75 0.75 0.5 0.5 16.0 20.0 2.5 2.5 1.0 1.0 0.5 0.5 LSB2 LSB2 T T T T T T T T T T T Freescale Semiconductor 31 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Table 16. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD 8 MHz) Preliminary Electrical Characteristics Table 16. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD 8 MHz) (continued) Characteristic Zero-Scale Error Conditions1 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Full-Scale Error 16-bit differential mode 16-bit single-ended mode 13-bit differential mode 12-bit single-ended mode 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Quantization Error 16-bit modes <13-bit modes 16-bit differential mode Avg=32 Avg=16 Avg=8 Avg=4 Avg=1 ENOB 16-bit single-ended mode Avg=32 Avg=16 Avg=8 Avg=4 Avg=1 -- -- -- -- -- 13.2 12.8 12.6 12.3 11.5 -- -- -- -- -- EQ EFS Symb EZS Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12.8 12.7 12.6 12.5 11.9 Typ2 4.0 4.0 0.7 0.7 0.4 0.4 0.2 0.2 +10/0 +14/0 1.0 1.0 0.4 0.4 0.2 0.2 -1 to 0 -- 14.2 13.8 13.6 13.3 12.5 Max +32/-24 +24/-16 2.5 2.0 1.0 1.0 0.5 0.5 +42/-2 +46/-2 3.5 3.5 1.5 1.5 0.5 0.5 -- 0.5 -- -- -- -- -- Bits LSB2 D LSB2 Unit LSB2 C T T T T T T T T VADIN = VDDAD Comment VADIN = VSSAD Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages C Effective Number of Bits Fin = Fsample/100 D Signal to Noise plus Distortion See ENOB SINAD SINAD = 6.02 ENOB + 1.76 dB Total Harmonic Distortion 16-bit differential mode Avg=32 THD 16-bit single-ended mode Avg=32 -- -- -91.5 -85.5 -74.3 dB -- C D Fin = Fsample/100 32 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 16. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDAD, > 1.8, VREFL = VSSAD 8 MHz) (continued) Characteristic Spurious Free Dynamic Range Conditions1 16-bit differential mode Avg=32 SFDR 16-bit single-ended mode Avg=32 -- 86.2 -- Symb Min Typ2 Max Unit C C dB D Fin = Fsample/100 Comment Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 75.0 92.2 -- Input Leakage Error all modes EIL IIn * RAS mV D IIn = leakage current (refer to DC characteristics ) Temp Sensor Slope Temp Sensor Voltage 1 2 -40C - 25C 25C - 125C 25C -- m -- VTEMP25 -- 1.646 1.769 701.2 -- -- -- mV/x C C mV C All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD Typical values assume VDDAD = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3 1 LSB = (V N REFH - VREFL)/2 3.10 # MCG and External Oscillator (XOSC) Characteristics Table 17. MCG (Temperature Range = -40 to 105C Ambient) Rating Symbol tirefst factory trimmed at VDD=3.0 V and temp=25C user trimmed Low range (DRS=00) Mid range (DRS=01) High (DRS=10) range1 Min -- -- 31.25 fdco_t 16 32 40 fdco_res_t -- -- -- fdco_t -- tfll_acquire tpll_acquire -- -- 0.5 -- -- 1 1 1 Typical 55 31.25 -- -- -- -- 0.1 0.2 1.0 Max 100 -- 39.0625 20 40 60 0.2 0.4 2 %fdco C C D %fdco MHz Unit s C D C C C C C C C p 1 Internal reference startup time Average internal reference frequency DCO output frequency range trimmed 2 fint_ft kHz 3 Resolution of trimmed DCO output 4 frequency at fixed voltage and temperature Total deviation of trimmed DCO 5 output frequency over voltage and temperature Acquisition time with FTRIM without FTRIM over voltage and temperature over fixed voltage and temp range of 0 - 70 C FLL2 PLL3 6 ms Freescale Semiconductor 33 Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 17. MCG (Temperature Range = -40 to 105C Ambient) (continued) # 7 Rating Long term Jitter of DCO output clock (averaged over 2mS interval) 4 Symbol CJitter fvco fpll_ref fpll_jitter_625 ns Min -- 7.0 1.0 -- 1.49 4.47 -- -- (3/5) x fint_t (16/5) x fint_t Typical 0.02 -- -- 0.5664 -- -- -- -- -- -- Max 0.2 55.0 2.0 -- 2.98 5.97 tfll_acquire+ 1075(1/fint_t) tpll_acquire+ 1075(1/fpll_ref) -- -- Unit %fdco MHz MHz %fpll % C C D D D D D D Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 8 VCO operating frequency 9 PLL reference frequency range 10 Jitter of PLL output clock measured Long term over 625ns 5 Entry6 Exit7 FLL 12 Lock time PLL 13 14 1 2 11 Lock frequency tolerance Dlock Dunl tfll_lock tpll_lock floc_low floc_high s D kHz kHz D D Loss of external clock minimum frequency - RANGE = 0 Loss of external clock minimum frequency - RANGE = 1 3 4 5 6 This should not exceed the maximum CPU frequency for this device. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps CAN Bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock. Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. 7 34 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics Table 18. XOSC (Temperature Range = -40 to 105C Ambient) Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 35 # Characteristic * Low range (RANGE = 0) flo * High range (RANGE = 1), * FEE or FBE mode 2 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) * High range (RANGE = 1), * High gain (HGO = 1), * FBELP mode * High range (RANGE = 1), * Low power (HGO = 0), * FBELP mode 2 Load capacitors Feedback resistor 3 High range (1 MHz to 16 MHz) Series resistor -- Low range 4 High Gain (HGO = 1) * Low Gain (HGO = 0) * High Gain (HGO = 1) 5 Series resistor -- High range 8 MHz 4 MHz 1 MHz Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) High range, high gain (RANGE = 1, HGO = 1) 1 2 3 4 5 o Symbol Min Typ1 Max Unit 32 1 -- -- 38.4 5 kHz MHz fhi fhi 1 -- 16 MHz fhi C1 C2 1 -- 8 MHz See Note 3 -- -- -- -- M -- -- k -- 100 -- Low range (32 kHz to 38.4 kHz) RF -- 10 1 0 Low Gain (HGO = 0) RS RS -- -- -- -- 0 0 0 200 400 5 15 0 10 20 -- -- k t CSTL -- -- 6 Crystal start-up time 4, 5 ms -- -- tCSTH -- Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. See crystal or resonator manufacturer's recommendation. This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 3.11 Mini-FlexBus Timing Specifications Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only devices up to a maximum bus frequency of 25.1666 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple chip-select based interface can be used. All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency. The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output clock (MB_CLK). All other timing relationships can be derived from these values. Table 19. Mini-FlexBus AC Timing Specifications Num -- MB1 MB2 MB3 MB4 MB5 1 2 C -- D T D T D Characteristic Frequency of Operation Clock Period Output Valid Output Hold Input Setup Input Hold Min -- 39.73 -- 1.0 22 10 Max 25.1666 -- 20 -- -- -- Unit MHz ns ns ns ns ns Notes -- -- 1 1 2 2 Specification is valid for all MB_A[19:0], MB_D[7:0], MB_CS[1:0], MB_OE, MB_R/W, and MB_ALE. Specification is valid for all MB_D[7:0]. 36 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics S0 S1 S2 S3 S0 MB1 MB3 ADDR[19:0] FB_A[19:16] 8-bit Non-Mux'd Bus FB_D[7:0] MB2 ADDR[31:24] MB5 DATA[7:0] MB4 FB_AD[19:16] 16-bit Mux'd Bus FB_AD[15:0] ADDR[15:0] ADDR[19:16] DATA[15:0] FB_R/W FB_ALE FB_CSn, FB_OE Figure 9. Mini-FlexBus Read Timing S0 S1 S2 S3 S0 FB_CLK MB1 MB3 ADDR[19:8] MB2 FB_AD[19:8] 8-bit Non-Mux'd Bus FB_AD[7:0] FB_AD[19:16] 16-bit Mux'd Bus FB_AD[15:0] FB_R/W FB_ALE FB_CSn FB_OE ADDR[15:0] ADDR[7:0] DATA[7:0] ADDR[19:16] DATA[15:0] Figure 10. Mini-FlexBus Write Timing 3.12 AC Characteristics This section describes ac timing characteristics for each peripheral system. Freescale Semiconductor 37 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages FB_CLK Preliminary Electrical Characteristics 3.12.1 Control Timing Table 20. Control Timing Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages # 1 Symbol fBus Parameter Bus frequency (tcyc = 1/fBus) VDD 1.8 V VDD > 2.1 V VDD > 2.4 V Min Typical1 Max C Unit MHz dc dc dc 800 100 66 x tcyc 500 100 -- -- -- 990 (TBD) -- -- -- -- 10 20 25.165 D D D s ns ns ns ns 2 3 4 5 6 tLPO textrst trstdrv tMSSU tMSH Internal low-power oscillator period External reset pulse width2 (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width * Asynchronous path2 * Synchronous path3 KBIPx pulse width * Asynchronous path2 * Synchronous path3 Port rise and fall time (load = 50 pF)4, Low Drive Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 1500 -- -- -- -- D D D D D 7 tILIH, tIHIL 100 1.5 x tcyc 100 1.5 x tcyc -- -- D ns 8 9 tILIH, tIHIL tRise, tFall -- -- D ns ns -- -- -- -- 11 35 40 75 -- -- -- -- D D D D Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40 C to 105 C. 1 2 38 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics RESET PIN Figure 11. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 12. IRQ/KBIPx Timing 3.12.2 TPM Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 21. TPM Input Timing # 1 2 3 4 5 C -- -- D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width tTPMext tclkh Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit MHz tcyc tcyc tcyc tcyc TPMxCLK tclkl Figure 13. Timer External Clock Freescale Semiconductor 39 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages textrst Preliminary Electrical Characteristics tICPW TPMxCHn TPMxCHn tICPW Figure 14. Timer Input Capture Pulse 3.13 SPI Characteristics Table 22 and Figure 15 through Figure 18 describe the timing requirements for the SPI system. Table 22. SPI Timing No.1 1 SPSCK period 2 Enable lead time 3 Enable lag time 4 Clock (SPSCK) high or low time 5 Data setup time (inputs) 6 Data hold time (inputs) 7 8 9 Slave access time3 Slave MISO disable time4 Master Slave Master Slave Master Slave tWSPSCK tcyc - 30 tcyc - 30 15 15 0 25 -- -- 1024 tcyc -- -- -- -- -- 1 1 ns ns ns ns ns ns tcyc tcyc D Master Slave tLag 1/2 1 -- -- tSPSCK tcyc D Master Slave tLead 1/2 1 -- -- tSPSCK tcyc D Master Slave tSPSCK 2 4 2048 -- tcyc tcyc D Characteristic2 Operating frequency Master Slave fop fBus/2048 0 fBus/2 fBus/4 Hz Hz D Symbol Min Max Unit C tSU tSU tHI tHI ta tdis D D D D 40 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics Table 22. SPI Timing (continued) No.1 10 Data hold time (outputs) 11 Rise time 12 Fall time 13 1 2 3 4 Characteristic2 Data valid (after SPSCK edge) Master Slave Master Slave Input Output Input Output Symbol tv Min -- -- 0 0 -- -- -- -- Max 25 25 -- -- tcyc - 25 25 tcyc - 25 25 Unit ns ns ns ns ns ns ns ns C D Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 41 tHO D tRI tRO tFI tFO D D Numbers in this column identify elements in Figure 15 through Figure 18. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Time to data active from high-impedance state. Hold time to high-impedance state. SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 11 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 12 2 5 4 3 5 4 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 15. SPI Master Timing (CPHA = 0) Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics SS(1) (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 11 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 12 BIT 6 . . . 1 LSB OUT LSB IN 3 NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 16. SPI Master Timing (CPHA = 1) SS (INPUT) 2 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT) NOTE: 3 5 4 5 4 11 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 12 SLAVE LSB OUT SEE NOTE 9 1. Not defined, but normally MSB of character just received Figure 17. SPI Slave Timing (CPHA = 0) 42 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics SS (INPUT) 2 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 11 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 12 BIT 6 . . . 1 SLAVE LSB OUT 9 3 NOTE: 1. Not defined, but normally LSB of character just received Figure 18. SPI Slave Timing (CPHA = 1) 3.14 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory chapter in the Reference Manual for this device (MCF51MM256RM). Table 23. Flash Characteristics # 1 2 3 4 5 6 7 8 9 10 1 Characteristic Supply voltage for program/erase -40C to 105C Supply voltage for read operation Internal FCLK frequency 1 Symbol Vprog/erase VRead fFCLK tFcyc 2 Min 1.8 1.8 150 5 Typical -- -- -- -- 9 4 4000 20,000 Max 3.6 3.6 200 6.67 Unit V V kHz s tFcyc tFcyc tFcyc tFcyc C D D D D P P P P C C Internal FCLK period (1/FCLK) Byte program time (random location) Byte program time (burst mode) Page erase time2 Mass erase time2 Program/erase TL to TH = -40C to + 105C T = 25C Data retention4 endurance3 2 tprog tBurst tPage tMass 10,000 -- tD_ret 15 -- 100,000 100 -- -- -- cycles years The frequency of this clock is controlled by a software setting. Freescale Semiconductor 43 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics 2 3 4 3.15 USB Electricals The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require additional information, this space would be used to communicate that information. Table 24. Internal USB 3.3 V Voltage Regulator Characteristics # 1 2 3 4 Characteristic Regulator operating voltage VREG output VUSB33 input with internal VREG disabled VREG Quiescent Current Symbol Vregin Vregout Vusb33in IVRQ Min 3.9 3 3 -- Typ -- 3.3 3.3 0.5 Max 5.5 3.6 3.6 -- Unit V V V mA C C P C C 44 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. Preliminary Electrical Characteristics 3.16 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 VREF Electrical Specifications Table 25. VREF Electrical Specifications Characteristic Supply voltage Temperature Output Load Capacitance Maximum Load Voltage Reference Output with Factory Trim. VDD = 3 V. Temperature Drift (Vmin - Vmax across the full temperature range) Aging Coefficient Powered down Current (Off Mode, VREFEN=0, VRSTEN=0) Bandgap only (MODE_LV[1:0] = 00) Low-Power buffer (MODE_LV[1:0] = 01) Tight-Regulation buffer (MODE_LV[1:0] = 10) Load Regulation MODE_LV = 10 Line Regulation (Power Supply Rejection) Symbol VDDA TA CL -- Vout Tdrift Ac I I I I -- DC AC Min 1.80 -40 -- -- 1.148 Max 3.6 105 100 10 1.152 10 (TBD) TBD 0.10 75 125 1.1 100 TBD -- Unit V C nf mA V mV1 ppm/year A A A mA V/mA mV C TBD dB C C D -- P T C C T T T C C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages -- -- -- -- -- -- -- -- See typical chart below. Table 26. VREF Limited Range Operating Requirements # 1 Characteristic Temperature Symbol TA Min 0 Max 50 Unit C C C Notes Table 27. VREF Limited Range Operating Behaviors # 1 Characteristic Voltage Reference Output with Factory Trim Symbol Vout Min TBD Max TBD Unit A C C Notes Freescale Semiconductor 45 Non-Disclosure Agreement Required Preliminary -- Subject to Change 46 Preliminary Electrical Characteristics TBD Figure 20. Typical Output vs. VDD Figure 19. Typical Output vs. Temperature Non-Disclosure Agreement Required Preliminary -- Subject to Change Freescale Semiconductor Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Preliminary Electrical Characteristics 3.17 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 TRIAMP Electrical Parameters Table 28. TRIAMP Characteristics 1.8-3.6 V, -40C~105C Characteristic1 Operating Voltage Supply Current (IOUT=0mA, CL=0) Low-power mode Supply Current (IOUT=0mA, CL=0) High-speed mode Input Offset Voltage Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current (0 ~ 50C) Input Bias Current (-40 ~ 105C) Input Common Mode Voltage Low Input Common Mode Voltage High Input Resistance Input Capacitances AC Input Impedance (fIN=100kHz) Input Common Mode Rejection Ratio Power Supply Rejection Ration Slew Rate (VIN=100mV) Low-power mode Slew Rate (VIN=100mV) High-speed mode Unity Gain Bandwidth (Low-power mode) 50pF Unity Gain Bandwidth (High-speed mode) 50pF DC Open Loop Voltage Gain (RL = 20 K) Load Capacitance Driving Capability Output Resistance Output Voltage Range Output Drive Capability Gain Margin Phase Margin Symbol VDD ISUPPLY ISUPPLY VOS VOS IOS IBIAS IBIAS VCML VCMH RIN CIN Min 1.8 -- -- -- -- -- -- -- 0 -- 500 -- -- 60 60 -- -- 0.15 -- -- -- -- 0.15 -- 20 45 Typ2 -- 80 350 3(TBD) TBD 270 300 (TBD) TBD -- -- -- -- 50 70 70 0.1 1 0.5 2 80 -- TBD -- 1.0 -- 55 Max 3.6 TBD TBD 10 -- TBD 500 (TBD) TBD -- VDD-1.4 -- 5 -- -- -- -- -- -- -- -- 50 -- VDD - 0.15 -- -- -- Unit V A A mV V/C pA pA pA V V M pF M dB dB V/s V/s MHz MHz dB pF V mA dB deg C C P P C C C C C D C T C C C C C C C C C C C T C Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 47 |XIN| CMRR PSRR SR SR GBW GBW AV CL(max) ROUT triout IOUT GM PM All parameters are measured at 3.3 V, CL= 47 pF across temperature -40 to + 105 C unless specified. Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Preliminary Electrical Characteristics 2 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Table 29. OPAMP Characteristics 1.8-3.6 V # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 Characteristics1 Operating Voltage Supply Current (IOUT=0mA, CL=0) Low-power mode Supply Current (IOUT=0mA, CL=0) High-speed mode Input Offset Voltage Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current Input Common Mode Voltage Low Input Common Mode Voltage High Input Resistance Input Capacitances AC Input Impedance (fIN=100kHz) Input Common Mode Rejection Ratio Power Supply Rejection Ration Slew Rate (VIN=100mV) Low-power mode Slew Rate (VIN=100mV) High speed mode Unity Gain Bandwidth Low-power mode Unity Gain Bandwidth High Speed mode DC Open Loop Voltage Gain Load Capacitance Driving Capability Output Resistance Output Voltage Range Output Drive Capability Gain Margin Phase Margin GPAMP settling time (low-power mode) (To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k) GPAMP settling time (low-power mode) GPAMP settling time (high-speed mode) (To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k) GPAMP settling time (high-speed mode) Symbol VDD ISUPPLY ISUPPLY VOS VOS IOS IBIAS VCML VCMH RIN CIN Min 1.8 -- -- -- -- -- -- 0.1 -- 500 -- -- 55 60 0.1 1 0.2 1 80 -- -- 0.15 0.5 20 45 -- -- -- -- Typ2 -- 40 420 (TBD) 3 1 TBD TBD -- -- -- -- TBD 65 65 -- -- -- -- 90 -- -- -- 1.0 -- 55 TBD TBD TBD TBD Max 3.6 55 (TBD) 450 (TBD) 10 -- TBD TBD -- VDD+0.1 -- 10 -- -- -- -- -- -- -- -- 100 1500 VDD-0.15 -- -- -- -- -- -- -- Unit V A A mV V/C pA pA V V M pF M dB dB V/s V/s MHz MHz dB pF V mA dB deg uS uS uS uS C C P P C C C C C T T T T C C C C C C C C C C C T C C C C C |XIN| CMRR PSRR SR SR GBW GBW AV CL(max) ROUT VOUT IOUT GM PM Tstartup Tstartup Tstartup Tstartup 2 All parameters are measured at 3.3 V, CL =4 7 pF across temperature -40 to + 105C unless specified. Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. 48 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages 3.18 OPAMP Electrical Parameters Freescale Semiconductor Preliminary Electrical Characteristics Non-Disclosure Agreement Required Preliminary -- Subject to Change 49 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages Ordering Information 4 Ordering Information Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages This section contains ordering information for the device numbering system. See Table 2 for feature summary by package information. 4.1 4.2 Device Numbering System Part Numbers Table 30. Orderable Part Number Summary Freescale Part Number MCF51MM256VML MCF51MM256VLL MCF51MM256VMB MCF51MM256VLK MCF51MM128VMB MCF51MM128VLK MCF51MM256CML MCF51MM256CLL MCF51MM256CMB MCF51MM256CLK MCF51MM128CMB MCF51MM128CLK Description MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM128 ColdFire Microcontroller MCF51MM128 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM256 ColdFire Microcontroller MCF51MM128 ColdFire Microcontroller MCF51MM128 ColdFire Microcontroller Flash / SRAM (Kbytes) 256K/32K 256K/32K 256K/32K 256K/32K 128K/32K 128K/32K 256K/32K 256K/32K 256K/32K 256K/32K 128K/32K 128K/32K Package 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP 81 MAPBGA 80 LQFP 104 MAPBGA 100 LQFP 81 MAPBGA 80 LQFP 81 MAPBGA 80 LQFP Temperature -40 to 105 C -40 to 105 C -40 to 105 C -40 to 105 C -40 to 105 C -40 to 105 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C 4.3 Package Information Table 31. Package Descriptions Package Type Low Quad Flat Package Low Quad Flat Package MAPBGA Package MAPBGA Package Abbreviation LQFP LQFP MAPBGA MAPBGA Designator LL LK ML MB Case No. 983-03 1418 1285-02 1662-01 Document No. 98ASS23308W 98ASS23174W 98ARH98267A 98ASA10670D Pin Count 100 80 104 81 4.4 Mechanical Drawings Table 31 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MCF51MM256/128 Product Summary pages at http://www.freescale.com. 50 Freescale Semiconductor Non-Disclosure Agreement Required Preliminary -- Subject to Change Revision History 5 Revision History Table 32. Revision History Revision 0 Date March/April 09 Initial Draft * * * * Revised to follow standard template. Removed extraneous headings from the TOC. Corrected units for Monotoncity to be blank in for the DAC specification. Updated ADC characteristic tables to include 16-Bit SAR in headings. Description This section lists major changes between versions of the MCF51MM256 Data Sheet. 1 July 09 2 July 09 * Changed MCG (XOSC) Electricals Table - Row 2, Average Internal Reference Frequency typical value from 32.768 to 31.25. * Updated Thermal Characteristics table. Reinserted the 81 and 104 MapBGA devices. * Revised the ESD and Latch-Up Protection Characeristic description to read: Latch-up Current at TA = 125C. * Changed Table . DC Characteristics rows 2 and 4, to 1.8 V, ILoad = -600 mA conditions to 1.8 V, ILoad = 600A respectively. * Corrected the 16-bit SAR ADC Operating Condition table Ref Voltage High Min value to be 1.13 instead of 1.15. * Updated the ADC electricals. * Inserted the Mini-FlexBus Timing Specifications. * Added a Temp Drift parameter to the VREF Electrical Specifications. * Removed the S08 Naming Convention diagram. * Updated the Orderable Part Number Summary to include the Freescale Part Number suffixes. * Completed the Package Description table values. * Changed the 80LQFP package drawing from 98ARL10530D to 98ASS23174W. MM256 uses 80LQFP12x12. * Updated electrical characteristic data. 3 April 10 Freescale Semiconductor 51 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages To view the latest drawing, either: * Click on the appropriate link in Table 31, or * Open a browser to the Freescale(R) website (http://www.freescale.com), and enter the appropriate document number (from Table 31) in the "Enter Keyword" search box at the top of the page. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009-2010. All rights reserved. Document Number: MCF51MM256 Rev. 3 04/2010 Non-Disclosure Agreement Required Preliminary -- Subject to Change Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCF51MM256 products in 81 and 104 MAPBGA packages and MCF51MM128 products in 81 MAPBGA packages |
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